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Description
No descriptionConfiguration
No ConfigurationOEM Model Description
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.Documents
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PREFERRED
SELLER
CATEGORY
Final Test
Last Verified: Over 60 days ago
Buyer pays 12% premium of final sale price
Key Item Details
Condition:
Used
Operational Status:
Unknown
Product ID:
104190
Wafer Sizes:
Unknown
Vintage:
Unknown
Have Additional Questions?
Logistics Support
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Money Back Guarantee
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Transaction Insured by Moov
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Refurbishment Services
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PREFERRED
SELLER
TERADYNE
J750EX
CATEGORY
Final Test
Last Verified: Over 60 days ago
Buyer pays 12% premium of final sale price
Key Item Details
Condition:
Used
Operational Status:
Unknown
Product ID:
104190
Wafer Sizes:
Unknown
Vintage:
Unknown
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
Description
No descriptionConfiguration
No ConfigurationOEM Model Description
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.Documents
No documents