The Deltamaster, introduced in 1990, is a high-performance system with the capability of testing up to 256 pins at data rates of up to 80 MHz or up to 128 pins at data rates of up to 160 MHz.

LTX/Trillium

DELTAMASTER

he Arraymaster and Micromaster, from Trillium are designed for VLSI tests of high-pin-count devices that involve complex timing and format schemes. The Micromaster is ideal for those who wish to generate test patterns manually. It has 128 I/O pins with 22-pf loading, timing accuracy of ± 250 ps with 20-ps resolution, a MUX data rate of 60 MHz, a picoammeter measuring module for every four pins, a 4K microinstruction controlled memory, a second 64K memory behind each pin, a serial scan mode, levels, timing and loads per pin, and time set switching on the fly.

MICROMASTER

The Delta/ST, introduced in 1995, incorporates Synchro mixed signal technology with Delta Series digital technology to address the test requirements of a new generation of devices with high performance analog signal interfaces to complex digital functions. These new devices are enabling the development of powerful, yet low cost consumer electronic products in areas such as multimedia and portable communications.

DELTA/ST

The Delta/STE, introduced in fiscal 1996, incorporates Synchro mixed signal technology with Delta Series digital technology to address the test requirements of a new generation of devices with high performance analog signal interfaces to complex digital functions. These new devices are enabling the development of powerful, yet low cost consumer electronic products in areas such as multimedia and portable communications.

DELTA/STE

 The Delta 50 is designed for the production test needs of microcontroller and digital IC manufacturers who do not require the sophisticated performance characteristics of the Delta 100. The Delta 50 has resource-per-pin architecture and is capable of testing 512 pins at data rates of up to 50 MHz or 256 pins at data rates of up to 100 MHz.

DELTA 50

The Delta 100 is specifically designed for testing high performance CISC (complex instruction set computing) and RISC (reduced instruction set computing) microprocessors and the ICs that make up the chip sets that are used with them. The Delta 100 has resource-per-pin architecture and can test up to 512 pins at data rates of up to 100 MHz. Timing accuracy of 150 pico seconds is a significant improvement over the Deltamaster and Micromaster test systems.

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DELTAMASTER

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